GCC 17 Compiler Merges Support For AVX10V1AUX

Landing today into the GCC 17 compiler codebase is initial support for AVX10V1AUX as the auxillary updates to AVX10.1 that are out of the cross-vendor AI Compute Extensions "ACE" initiative between AMD and Intel. AVX10V1AUX is a bridge between early AVX10 hardware and later AVX10.2 capabilities. AVX10V1AUX adds native VNNI INT8 and VNNI INT16 support, instruction borrowing, and other incremental changes. For some weeks now AMD engineers have been leading the work on AVX10V1AUX ISA support for GCC while today they were merged to GCC Git. The patches add in the AVX10V1AUX capabilities and exposed via the -mavx10v1aux compiler switch. The AVX10V1AUX capabilities aren't yet tied into any specific Intel/AMD processor generations in the compiler targeting. This commit to GCC adds in that initial AVX10V1AUX support.